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INTEGRATED CIRCUITS
DATA SHEET
PCF5001 POCSAG Paging Decoder
Product specification Supersedes data of 1995 Apr 27 File under Integrated Circuits, IC17 1997 Mar 04
Philips Semiconductors
Product specification
POCSAG Paging Decoder
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAMS PINNING FUNCTIONAL DESCRIPTION The PCF5001 supports two basic modes of operation The POCSAG paging code Modes and states of the decoder Decoding of the POCSAG data stream Generation of output signals Alerter Silent call storage and Repeat mode Duplicate Call Suppression LED indicator Vibrator output Start-up alert Serial communication interface Message data transfer Call Data output on LED Serial communication call data format Data conversion Memory Organization Description of the Special Programmed Function (SPF) bits 7.22 7.23 7.23.1 7.23.2 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.4 17 18 7.19 7.20 7.21
PCF5001
EEPROM Write operation EEPROM Read operation Read-back operation via Microcontroller Interface Voltage converter Test modes of the decoder Board test mode Pager Test Mode (Type Approval Mode) LIMITING VALUES DC CHARACTERISTICS DC CHARACTERISTICS (WITH VOLTAGE CONVERTER) AC CHARACTERISTICS TIMING CHARACTERISTICS PROGRAMMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING Introduction Reflow soldering Wave soldering LQFP SO Method (LQFP and SO) Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
1 FEATURES
PCF5001
* Serial microcontroller interface for display pager applications * Optional visual indication of received call data using a modified RS232 format * Level shifted microcontroller interface signals * Alert on low battery * Optional out-of-range indication. 2 APPLICATIONS
* Wide operating supply voltage range (1.5 to 6.0 V) * Extended temperature range: -40 to +85 C (between -40 to -10 C, minimum supply voltage restricted to 1.8 V) * Very low supply current (60 A typ. with 76.8 kHz crystal) * "CCIR radio paging Code No 1" (POCSAG) compatible * Programmable call termination conditions * 512 and 1200 bits/s data rates (2400 bits/s with some restrictions), see Section 7.4 * Improved ACCESS(R) synchronization algorithm * Supports 4 user addresses (RICs) in two independent frames * Eight different alert cadences * Directly drives magnetic or piezo ceramic beeper * High level alert requires only a single external transistor * Optional vibrator type alerting * Silent call storage, up to eight different calls * Repeat alarm facility * Programmable duplicate call suppression * Interfaces directly to UAA2050T, UAA2080 and UAA2082 digital paging receivers * Programmable receiver power control for battery economy * On-chip non-volatile EEPROM storage * On-chip voltage converter with improved drive capability 4 ORDERING INFORMATION
* Alert-only pagers, display pagers * Telepoint * Telemetry/data receivers. 3 GENERAL DESCRIPTION
The PCF5001 is a fully integrated low-power decoder and pager controller. It decodes the CCIR radio paging Code No.1 (POCSAG-Code) at 512 and 1200 bits/s data rates. The PCF5001 is fabricated in SACMOS technology to ensure low power consumption at low supply voltages.
PACKAGE TYPE NUMBER NAME PCF5001T PCF5001H Note 1. When using IR reflow soldering it is recommended that the Drypack instructions in the "Quality Reference Handbook" (order number 9397 750 00192) are followed. SO28 LQFP32(1) DESCRIPTION plastic small outline package; 28 leads; body width 7.5 mm plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm VERSION SOT136-1 SOT358-1
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
5 BLOCK DIAGRAMS
PCF5001
handbook, full pagewidth
VSS 17
VDD 4
DO 26
DS 27
DI
5
DIGITAL INPUT FILTER
SERIAL DATA PROCESSOR
DATA OUTPUT CONTROL
CLOCK RECOVERY
DECODER AND ERROR CORRECTION CONTROL
EEPROM MEMORY
7 EEPROM CONTROL RE 14 RECEIVER ENABLE CONTROL SYNC CONTROL TIMING CONTROL ALERT GENERATION CONTROL 8 12 15 25 16 13 23
PD PS AH AL OR OM OL AI
X1 X2
9 10 OSCILLATOR CLOCK GENERATION
PCF5001T
VOLTAGE CONVERTER
POWER-ON RESET
TEST CONTROL
STATUS CONTROL
BATTERY LOW CONTROL
3
2
1
28
11
18
21 20 22 19
24
6
MCD454
CP
CN
V ref
FL
TS
TT
SR SK ON IE
BL
BS
Fig.1 Block diagram (SO28; SOT136-1).
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
handbook, full pagewidth
VSS 31
VDD 16
n.c. 2
n.c. 7
n.c. 20
n.c. 21
DO 10
DS 11
DI
17
DIGITAL INPUT FILTER
SERIAL DATA PROCESSOR
DATA OUTPUT CONTROL
CLOCK RECOVERY
DECODER AND ERROR CORRECTION CONTROL
EEPROM MEMORY
19 EEPROM CONTROL RE 28 RECEIVER ENABLE CONTROL SYNC CONTROL TIMING CONTROL ALERT GENERATION CONTROL 22 26 29 9 30 27 6
PD PS AH AL OR OM OL AI
X1 X2
23 24 OSCILLATOR CLOCK GENERATION
PCF5001H
VOLTAGE CONVERTER
POWER-ON RESET
TEST CONTROL
STATUS CONTROL
BATTERY LOW CONTROL
15
14
13
12
25
32
4
3
5
1
8
18
CP
CN
V ref
FL
TS
TT
SR SK ON IE
BL
BS
MLB045
Fig.2 Block diagram (LQFP32; SOT358-1).
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
6 PINNING PIN SYMBOL Vref PCF5001T (SOT136-1) 1 PCF5001H (SOT358-1) 13 DESCRIPTION
PCF5001
Microcontroller interface reference voltage input/output. The LOW level of pins FL, DS, DO, OR, BL, AI, ON, SK, SR and IE is related to the voltage on Vref. May be driven from an external negative voltage source or must be connected to VSS, if pins CN and CP are left open-circuit. When the on-chip voltage converter is used, this pin provides a doubled negative output voltage. Voltage converter external shunt capacitance, negative side. Connect the negative side of the shunt capacitor to this pin, if the on-chip voltage converter function is used. Voltage converter external shunt capacitor, positive side. Connect the positive side of the shunt capacitor to this pin, if the on-chip voltage converter function is used. Main positive power supply. This pin is common to all supply voltages and is referred to as 0 V (common). Serial data input (POCSAG code). The serial data signal train applied to this pin is processed by the decoder. Pulled LOW by an on-chip pull-down when the receiver is disabled (RE = LOW). Battery-low indication input. The decoder samples this input during synchronization scan, when it is in ON or SILENT status and the receiver is enabled (RE = HIGH). A battery-low condition is assumed, if the decoder detects four consecutive samples HIGH. An audible battery-low indication is made by the decoder, when operating in ON status. Normally LOW by the operation of an on-chip pull-down. EEPROM programming data input and output. Normally HIGH by the operation of an on-chip pull-up. During programming of the on-chip EEPROM, PD is a bidirectional data and control signal. EEPROM programming strobe input. Normally LOW by the operation of an on-chip pull-down. During programming of the on-chip EEPROM, PS is a unidirectional control input. Crystal oscillator input. Connect a 32768 Hz or 76800 Hz crystal and a biasing resistor between this pin and X2. In addition, provide a load capacitance to VDD, which may also be used for frequency tuning. Crystal oscillator output. Return connection for the external crystal and resistor at X1. Scan test mode enable input. Always LOW by operation of an on-chip pull-down. Alert HIGH-level output. This output can directly drive an external bipolar transistor to control HIGH-level alerting in conjunction with AL, by means of an alerter or beeper. LED indication output. This output can directly drive an external bipolar transistor to control the visual alert function by means of an LED. It may also be used for visual indication of received call data during call reception.
CN
2
14
CP
3
15
VDD DI
4 5
16 17
BS
6
18
PD
7
19
PS
8
22
X1
9
23
X2 TS AH
10 11 12
24 25 26
OL
13
27
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
PIN SYMBOL RE PCF5001T (SOT136-1) 14 PCF5001H (SOT358-1) 28 DESCRIPTION Receiver enable output. May be used to control the paging receiver power control input, to minimize power consumption. The decoder provides a HIGH-level at this pin, when receiver operation is requested. Each time the decoder does not require any input data at DI the receiver enable output is LOW. Alert LOW-level output. Open drain alert output in anti-phase to AH, to provide LOW-level alerting. HIGH-level alerting is generated in conjunction with AH. Vibrator output. This output can directly drive an external bipolar transistor to control a vibrator type alerter. Main negative supply voltage. Test mode enable input. Always LOW by operation of an on-chip pull-down. Interface enable input. While the interface enable input is active HIGH, operation of the ON, SK, SR, AI, BL and OR inputs and outputs is possible. When IE is LOW the inputs do not respond to applied signals and the outputs are made high-impedance. In alert-only pager mode the interface enable input does not have any effect on the operation of inputs ON, SK and SR, but IE must be referenced to LOW or HIGH. SILENT state control input. The SILENT control input selects the decoder ON status (LOW-level) or SILENT status (HIGH-level), if the ON input is active HIGH. An on-chip pull-up is provided, if the decoder has been programmed for `alert-only pager' mode, whereby the pull-up is disabled for display pager mode. In `display pager' mode status change is possible if the interface enable input (IE) is HIGH and the status is latched on the falling edge of IE. Status request and reset input. A HIGH-going pulse on this input causes (a) status indication cadence to be generated, if the decoder is not alerting or (b) resetting of a call alert, repeated call alert or battery-low alert, if active or (c) triggers the call store re-alert facility, if repeat mode is active. In `display pager' mode operation of SR is possible only if the interface control input is active. Normally LOW by the operation of an on-chip pull-down. On/off control input. The on/off control input selects the decoder ON status (HIGH-level) or OFF status (LOW-level). An on-chip pull-up resistor is provided, if the decoder has been programmed for `alert-only pager' mode, but the pull-up resistor is disabled for `display pager' mode. In `display pager' mode, status change is possible if the interface enable input (IE) is HIGH and the status is latched on the falling edge of IE. Alarm input. A HIGH-level on this input causes generation of a continuous HIGH-level alert via AH and AL outputs, if the decoder operates in ON status or OFF status. In addition, the LED output is active independent from the decoder status, but in accordance with AI. Pulsing the input may be used to modulate the alert and LED indication. Normally LOW in `alert-only pager' mode by operation of an on-chip pull-down.
AL
15
29
OM VSS TT IE
16 17 18 19
30 31 32 1
SK
20
3
SR
21
4
ON
22
5
AI
23
6
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
PIN SYMBOL BL PCF5001T (SOT136-1) 24 PCF5001H (SOT358-1) 8 DESCRIPTION Battery-low indication output. If the decoder encounters a battery-low condition a battery-low output latch is set HIGH. The battery-low output latch may be tested for a battery-low condition, whenever the interface enable input (IE) is active (HIGH), otherwise the battery-low output is made high-impedance. The battery-low output latch is reset only, by switching the decoder to OFF status. Out-of-range indication output. Whenever the decoder detects an out-of-range condition an out-of-range output latch is set HIGH after expiry of the programmed out-of-range hold-off time selected by means of special programming (SPF06 and SPF07) of the EEPROM. The out-of-range latch may be tested for an out-of-range condition, whenever the interface enable input (IE) is active (HIGH), otherwise the out-of-range output is made high-impedance. The out-of- range output is reset by detection of a valid data transmission or by switching the decoder to OFF status. Serial interface data output. During normal decoder operation, accepted calls and possibly subsequent message data are serially output via this pin in conjunction with the data strobe output (DS). This pin is also used to output the EEPROM contents upon special command, if the decoder is programmed for display pager. Serial interface data strobe output. Provides a clock signal for the received call data and EEPROM data appearing at the data output (DO). Each time this output is LOW the data at DO is valid. Additional start and stop conditions allow easy identification of data sequence start and end. Frequency reference output. When programmed for `display pager' mode, this output provides a clock reference with 16384 or 32768 Hz per second, selected by SPF32. See Chapter 7. Not connected.
OR
25
9
DO
26
10
DS
27
11
FL
28
12
n.c.
-
2, 7, 20, 21
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
handbook, halfpage
Vref CN CP VDD DI BS PD PS X1
1 2 3 4 5 6 7 PCF5001T 8 9
28
FL
VSS
RE
AH 26
OL
TT
27 DS 26 DO 25 OR 24 BL
index corner IE n.c. 1 2 3 4
32
31
30
29
28
27
25
TS
AL
handbook, halfpage
OM
24 X2 23 X1 22 PS 21 n.c. PCF5001H 20 n.c. 19 PD 18 BS 17 DI
23 AI 22 ON 21 SR 20 SK 19 18 17 16 15
MCD455 - 1
SK SR ON AI n.c. BL
5 6 7 8
X2 10 TS 11 AH 12 OL 13 RE 14
IE TT VSS
10
11
12
13
14
15
16
9
OR
DO
DS
V ref
CN
CP
FL
AL
Fig.3 Pin configuration PCF5001T (SOT136-1).
Fig.4 Pin configuration PCF5001H (SOT358-1).
7
FUNCTIONAL DESCRIPTION
The PCF5001 is a very low power Decoder and Pager Controller specifically designed for use in new generation radio pagers. The architecture of the PCF5001 allows for flexible application in a wide variety of radio pager designs. The PCF5001 is fully compatible with "CCIR radio paging Code Number 1" (also known as the POCSAG code) operating at the originally specified 512 bits/s data rate, and also at the newly specified 1200 bits/s data rate (2400 bits/s operation is also possible). The PCF5001 also offers features which extend the basic flexibility and efficiency of this code standard. 7.1 The PCF5001 supports two basic modes of operation
In display pager mode the state input logic is switched to a bus interface structure. Received calls and messages are transferred to an external microcontroller via the serial microcontroller interface. A built-in voltage converter with increased drive capabilities can supply doubled supply voltage output, and appropriate logic level shifting on microcontroller interface signals is provided. Upon reception of valid calls one of eight different call cadences is generated; upon status interrogation status indication tones make the current status of the decoder available to the user. On-chip non-volatile 114-bit EEPROM storage is provided to hold up to four user addresses, two frame numbers and the programmed decoder configuration. Synchronization to the input data stream is achieved using the improved ACCESS(R) algorithm, which allows for data synchronization and re-synchronization without preamble detection while minimizing battery power consumption by receiver power control. One of four error correction algorithms is applied to the received data to optimize the call success rate.
In alert-only pager mode only a minimum number of external components are required to build a complete tone-only pager. Selection of operating states ON, OFF or SILENT is achieved using a slider switch interface.
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VDD
OM
MLB048
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.2 The POCSAG paging code
PCF5001
Four different call types (`numeric', `alphanumeric' and two `alert only' types) can be distinguished. The call type is determined by two function bits in the address codeword (bits 20 and 21). Alert-only calls consist only of a single address codeword. Numeric and alphanumeric calls have message codewords following the address. A message causes the frame structure to be temporarily suspended. Message codewords are sent until the message is completed, with only the sync words being transmitted in their expected positions. Message codewords are identified by an MSB at logic 1 and are coded as shown in Fig.5. The message information is stored in a 20-bit field (bits 2 to 21). The standard data format is determined by the call type: 4 bits per digit for numeric messages and 7 bits per (ASCII) character for alphanumeric messages. Each codeword is protected against transmission errors by 10 CRC check bits (bits 22 to 31) and an even-parity bit (bit 32). This permits correction of a maximum of 2 random errors or up to 3 errors in a burst of 4 bits (a 4-bit burst error) per codeword.
A transmission using the "CCIR Radio paging Code No. 1" (POCSAG code) is constructed in accordance with the following rules (see Fig.5). The transmission is started by sending a preamble, consisting of at least 576 continuously alternating bits (10101010...). The preamble is followed by an arbitrary number of batch blocks. Only complete batches are transmitted. Each batch comprises 17 codewords of 32 bits each. The first codeword is a synchronization codeword with a fixed pattern. The sync word is followed by 8 frames (0 to 7) of 2 codewords each, containing message information. A codeword in a frame can either be an address, message or idle codeword. Idle codewords also have a fixed pattern and are used to fill empty frames or to separate messages. Address codewords are identified by an MSB at logic 0 and are coded as shown in Fig.5. A user address or RIC consists of 21 bits. Only the upper 18 bits are encoded in the address codeword (bits 2 to 19). The lower 3 bits designate the frame number (0 to 7) in which the address is transmitted.
handbook, full pagewidth
PREAMBLE
BATCH 1
BATCH 2
BATCH 3
LAST BATCH
10101 . . . 10101010
SYNC | CW CW | CW CW | . . . . . | CW CW
FRAME 0 FRAME 1 FRAME 7
Address code-word
0
18-bit address
2 function bits
10 CRC bits
P
Message code-word
1
20-bit message
10 CRC bits
P
MCD456
Fig.5 POCSAG code structure.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.3 Modes and states of the decoder
PCF5001
and the decoder. Upon detection of a valid call, address and message information are transferred to the external microcontroller using the serial microcontroller interface. In addition, appropriate call alert cadences are generated. If the decoder is in one of the two operating modes, it is always in one of the following three internal states: * OFF status. This is the power saving, inactive status of the PCF5001. The paging receiver is disabled, no decoding of input data takes place. However, the crystal oscillator is kept running to ensure that scanning of the status inputs/status switch is maintained to allow changing into one of the following two active states. * ON status. This is the normal active status of the decoder. Incoming calls are compared with the user addresses stored in the internal EEPROM. Upon detection of valid calls, alert cadences and LED indication are generated and data is shifted out at the serial microcontroller interface. * SILENT status. The SILENT status is the same as the ON status with the exception that valid calls no longer cause generation of call alert cadences. Instead, if programmed as `alert-only pager', the decoder stores up to eight different calls and generates appropriate alert cadences after the decoder has been put back into the ON status. However, special SILENT override calls will cause generation of alert cadences, if enabled. The decoder operating status is selected as indicated in Table 1. When programmed for `alert-only pager' a switch debounce period is applied to the status inputs. For status change and status interrogation in `display pager' mode, see Figs 6 and 7.
The PCF5001 supports two basic operating modes: * `Alert-only pager' mode * `Display pager' mode. Two further modes, the programming mode and the test mode, are implemented to program and verify the EEPROM contents and to support pager production and approval tests, respectively. In `alert-only pager' mode no external microcontroller is required, see Fig.22. A three position slider switch interface is provided to select the internal state of the decoder. The decoder performs regular scanning of the switch inputs to detect a status change. A push-button interface is provided on the SR input, which is used as input for user acknowledgment actions and status interrogation. Upon reception of valid calls, tone alert cadences are generated. A call storage is provided to store calls received while operating in SILENT status and to recall cadences upon `repeat' mode operation. The voltage doubler and the frequency reference output are disabled in this mode. In `display pager' mode the PCF5001 operates as decoder and pager controller in combination with an external microcontroller (see Fig.23). The internal states of the decoder are determined by appropriate logic levels on the status inputs. A bus type interface structure is used to interface the decoder to the microcontroller. The decoder's on-chip voltage converter provides doubled supply voltage output to provide a higher supply voltage to the microcontroller and any additional hardware. The logic levels of the interface's input and output signals are level shifted to allow for direct coupling between microcontroller Table 1 Truth table for decoder operating status SK INPUT 0 1 0 1 OFF
ON INPUT 0 0 1 1 Note
OPERATING STATUS OFF (EEPROM transfer mode; note 1) ON SILENT
1. The EEPROM transfer mode applies to `display pager' mode only.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
IE
ON SK
INTERNAL STATUS
t STP
t STD
t STD t IEH
t STH
MCD457 - 1
Fig.6 Status change in display pager mode.
IE
SR
t
STP
t
STH
t
SPD
t
IEH
t
STH
MCD458
Fig.7 Status interrogation in display pager mode.
7.4
Decoding of the POCSAG data stream
The POCSAG coded input data stream is first noise filtered by a digital filter. From the filtered data a sampling clock synchronous to the data rate is derived. The PCF5001 supports 512 bits/s and 1200 bits/s data rates. This results in a 512 Hz or 1200 Hz sampling clock frequency, respectively. Synchronization on the POCSAG code structure is performed using the improved Philips ACCESS(R) algorithm, which employs a state machine with six internal states.
A data rate of 2400 bits/s is possible if an external clock generator of 153.6 kHz is connected to X1. The minimum supply voltage is then -1.8 V. The receiver enable output is activated a period equal to tRXON before the input data is actually needed. The decoder has first to achieve bit and word synchronization before it can receive calls. The algorithm searches first for the preamble and then for synchronization codeword patterns.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
This is carried out for the duration of 3 batches in power-on mode or 1 batch (=preamble duration) in preamble receive mode. Error correction algorithms are applied to the data before it is compared with preamble and synchronization codeword patterns. The synchronization process is terminated and thus data receive mode is entered as soon as synchronization codewords are seen at the beginning of each batch. The decoder handles loss of synchronization in three steps: 1. If the decoder fails to detect the synchronization pattern at the beginning of the current batch it continues data reception as normal. This data fail mode is signalled in the message output when an address codeword was received, as shown in Table 4. 2. If also at the beginning of the next batch no synchronization codeword can be detected, the algorithm assumes a small bit shift in the fade recovery mode and performs more synchronization codeword checks around the expected position for the following 15 batches. Call reception is suspended. 3. If it fails to re-synchronize in the `fade recovery' mode, the carrier off mode is selected, in which the decoder attempts to regain synchronization by bit-wise shifting its synchronization scan window. Using this technique re-synchronization is obtained within a continuous data stream of at least 18 batches without preamble detection. Table 2 Call termination on error SPF13 X(1) 0 1 CALL TERMINATION EVENT
PCF5001
In `data receive' mode, the input data stream is sampled at the synchronization codeword position and the programmed frame positions. The received codewords are error corrected and then, if address codewords, compared with the stored user addresses related to that frame. On detection of a valid call, the decoder performs the following three operations: 1. Set a store for call alert cadence generation according to the combination of the function bits in the accepted address codeword. The call alert cadence will not be generated before the call has been terminated. 2. Keep the receiver enable output (RE) active and receive subsequent message codewords, until any of the call termination criteria are fulfilled. 3. Trigger the serial message transfer by sending a start condition and transfer deformatted message codewords as attached to the address codeword via the serial microcontroller interface to an external microcontroller, followed by a stop condition. Normally call termination is assumed, when a valid idle or address codeword is received. On reception of uncorrectable codewords, call termination takes place in accordance with conditions shown in Table 2.
SPF12 0 1 1 Note 1. X = don't care.
Any two consecutive codewords or the codeword directly following the address codeword uncorrectable. Any single codeword uncorrectable. Any two consecutive codewords uncorrectable.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.5 Generation of output signals
PCF5001
Table 3 shows the outputs which are used for special output indications, if the decoder operates in ON status. Remark: reception of special SILENT override calls causes the decoder to generate call alert indication via AL and AH even if it operates in SILENT status.
The PCF5001 provides output indications for call alert, repeat mode alert, out of range alert, battery-low alert, status indication alert and start-up alert. Some of the alert functions may be freely configured by programming of SPF bits within the EEPROM. Table 3 Output signals
OUTPUT ACTIVE(1) ALERT FUNCTION AL Start-up Status indication Call reception Repeat mode Out-of-range Battery-low Alarm input Note 1. Entries in parenthesis are not valid, if the decoder operates in SILENT status. 7.6 Alerter The call alert cadence is modulated according to the two function bits (FC) in the received address codeword, see Fig.9. Valid calls received on RIC B or RIC D cause the alerter frequency to be warbled by means of an additional 16 Hz and 1024 Hz signal (respective 1365 Hz for SPF31 = 1) as opposed to RIC A and RIC C where no alert frequency warble takes place. Thus, eight different call cadences are distinguishable. ON status interrogation by the status request and reset input (SR) the PCF5001 generates a status cadence at LOW-level, in accordance with the present internal decoder status (see Fig.10). When detecting a battery-low condition the PCF5001 provides a battery-low indication. Operating in ON status causes generation of a battery-low alert at HIGH-level for sixteen seconds or until terminated by pulsing SR. Operating in SILENT status or `repeat' mode the battery-low alert is stored and inhibited until switching to ON status. (yes) yes (yes) (SPF16) - (yes) (yes) AH - - (yes) (SPF16) - (yes) (yes) OL yes - yes SPF16 SPF15 - yes OM yes - SPF11 - - - - OR - - - - yes - - BL - - - - - yes -
The PCF5001 provides the AL and AH outputs for acoustical LOW-level and HIGH-level signalling. LOW-level alerting is provided by the AL output only. For HIGH-level alerting both, AL and AH are active in anti-phase. The square-wave output signals produce tone alert cadences by means of a magnetic or piezo ceramic beeper. The alert frequency, 2048 Hz or 2731 Hz square-wave, is selected by programming of SPF31. When valid calls are received while operating in ON status, the PCF5001 generates call alert cadences. The first four seconds are generated at LOW-level, a further twelve seconds are generated at HIGH-level. Alert tone generation and LED indication automatically terminate after sixteen seconds unless terminated by pulsing the status request and reset input (SR). Call alert generation is inhibited until completion of message codeword reception and the termination word is sent by the decoder. Call alert generation commences after an alert delay period, tALD, at the earliest, see Fig.8. Call alert deletion is possible during the alert delay period.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
DO DS
EOT
STP
AL AH OL
CALL1
CALL2
t
ALD
t
ALD
MCD459
Fig.8 Call alert delay.
cadence 1 (FC = 00) t ALP t ALC cadence 2 (FC = 01) t ALP t ALC cadence 3 (FC = 10) t ALP t ALC cadence 4 (FC = 11) t ALP t ALC t ALC t ALP
MCD460
t ALP
t ALP
Fig.9 Call alert cadences.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
ON
t STON
OFF
t STON
t STOF
SILENT
t STON
t STOF
MCD461
Fig.10 Status indication cadences.
7.7
Silent call storage and repeat mode
When programmed for alert only pager the PCF5001 provides a call alert storage for storing of call alerts received during SILENT status or for call alerts which caused the decoder to enter repeat mode. Call alert is not stored, when call indication is terminated by action of the status request and reset input (SR). Allowing the call indication to time-out by expiration of a sixteen second alert operation causes the `repeat' mode to be entered, while operating in ON status or SILENT status. Such call alerts are stored for later repeated call alert on interrogation by the user. When `repeat' mode has been entered and the decoder operates in ON status, the repeat call store is interrogated by pulsing the status request and reset input (SR) or on switching to ON status if the decoder operates in SILENT status. When SILENT override calls are received, which entered the `repeat' mode, interrogation of repeat call store operates as in decoder ON status. After interrogation of repeat call store and subsequent generation of all stored call alerts the call store is cleared and the `repeat' mode is terminated. When programmed by means of SPF16, a repeat alert cadence is generated periodically, whenever `repeat' mode has been entered. Operating in ON status causes the repeat alert cadence to be generated at HIGH-level and warbled by means of an additional 16 Hz and 1024 Hz signal (respective 1365 Hz for SPF31 = 1) as shown in Fig.11. The LED output indicates the same alert cadence and alert warble. In SILENT status only the LED output is active. 1997 Mar 04 16
No call alert storage occurs when the decoder is programmed for `display pager' mode. 7.8 Duplicate Call Suppression
The PCF5001 provides a Duplicate Call Suppression with time-out facility, to identify duplicate call reception. When selected by programming of SPF14, the PCF5001 inhibits any duplicate call alert in `alert-only pager' mode. In `display pager' mode, duplicate call indication is achieved only via the serial microcontroller interface. A call is assumed to be duplicate if its address and function bit setting is equal to the latest received call, which initialized the call address and function bit reference. The Duplicate Call Suppression time-out is selectable by programming of SPF06 and SPF07. 7.9 LED indicator
The PCF5001 provides for visual signalling using a LED via output OL. Call alert indication is provided by the LED with the same cadence and warble modulation as for the alerter outputs AL and AH. Call alert indication occurs in ON and SILENT status and automatically terminates after sixteen seconds time-out unless terminated by pulsing the status request and reset input (SR). When detecting an out-of-range condition and enabled by programming of SPF15, the LED output provides an out-of-range indication as shown in Fig.12.
Philips Semiconductors
Product specification
POCSAG Paging Decoder
The LED output can be made to provide message data by programming SPF17. Alert signals are inhibited during message data transfer.
PCF5001
When changing from OFF to SILENT status, the start-up alert will be indicated on the LED output and the vibrator output OM.
AL AH OL
AL OL OM
t RCR
t RPT
MCD462
t
MCD464
SUA
Fig.11 Repeat alert cadence.
Fig.13 Start-up alert.
7.12
Serial communication interface
To transmit any call message data received to an external microcontroller for post-processing, a serial communication interface has been provided by a serial data output signal DO and a data strobe signal DS as shown in Fig.14.
t ORD t ORA
MCD463
Upon interrogation the PCF5001 is also able to transfer EEPROM contents via the serial communication interface, see Section 7.21. 7.13 Message data transfer
Fig.12 Out-of-range indication. 7.10 Vibrator output
The PCF5001 provides the OM output for activating a vibrator-type alerter for call alert indication. The vibrator output is enabled by programming of SPF11. Calls received while operating in SILENT status cause activation of the vibrator output for the normal call alert cadence or until terminated by operation of the status request and reset input (SR). SILENT override calls, calls received in decoder ON status and repeated call alerts are alerted normally by the AL and AH outputs. 7.11 Start-up alert
The transfer of message data via DO and DS is organized in 8-bit words providing additional start and stop conditions as shown in Fig.15. On reception of a valid call address the PCF5001 generates a start condition and outputs an address word as shown in Fig.15a. The address word indicates call address, function bit setting and decoder flags as shown in Table 4. Message codewords received and concatenated to a valid call address are transferred after completion of the address word. The message bits received in the message codewords are split into blocks and are converted to obtain the message words. The message words comprise an error flag to indicate message words, which are derived from uncorrectable message codewords as shown in Table 5. Message data is output at a rate of 2048 bits/s with a minimum delay of 2 bits between consecutive message words.
To indicate the establishment of operational condition whenever the decoder status has been changed from OFF to ON or SILENT status, the PCF5001 provides a start-up alert indication. Switching from OFF to ON status causes generation of a start-up alert cadence at LOW-level and on the LED output OL (see Fig.13).
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17
Philips Semiconductors
Product specification
POCSAG Paging Decoder
Termination of call reception causes a termination word to be transferred, which indicates successful or unsuccessful call termination as shown in Table 6.
PCF5001
Serial data transfer for a received call ends with a stop condition as shown in Fig.15c.
START OF TRANSFER
start condition A0 address word A1 A2 A3 A4 A5 A6 A7 1st message word
DO
DS
MESSAGE TRANSFER
message word N-1 DO message word N Mn0 Mn1 Mn2 Mn3 Mn4 Mn5 Mn6 Mn7 message word N+1
DS
END OF TRANSFER
last message word DO T0 T1 T2 termination word T3 T4 T5 T6 T7 stop condition
DS
MEA254 - 1
Fig.14 Call data transfer on the serial communication interface.
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18
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
handbook, full pagewidth
DO
DS t DOS t ST
a.
DO
DS
t TDO
t DSW t DSD
t DOH
t DOS
b.
DO
DS t
DOH t SP
MEA253 - 2
c.
a. Start condition. b. Data bit. c. Stop condition.
Fig.15 Serial communication interface timing.
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19
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.14 Call Data output on LED
PCF5001
(respectively 1 and 0). The data format is shown in Fig.16. No alert signals will appear on OL during message data transfer. Consecutive message words have a minimum separation of 1 start bit and 1 stop bit.
When enabled by programming of SPF17 = 1, message data will appear on the LED output OL. The data format and timing are equal to the signal on DO, except that the start/stop conditions are replaced with start/stop bits
START OF TRANSFER
address word OL start bit A0 A1 A2 A3 A4 A5 A6 A7 stop bit start bit message word N 1 1st message word
MESSAGE TRANSFER
message word N-1 OL start bit stop bit message word N Mn0 Mn1 Mn2 Mn3 Mn4 Mn5 Mn6 Mn7 start bit
MEA255 - 1
END OF TRANSFER
last message word OL stop bit start bit T0 T1 T2 termination word T3 T4 T5 T6 T7 stop bit
Fig.16 Call data transfer on the LED output.
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stop bit
Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.15 Serial communication call data format Address word format CALL ADDRESS BIT 4 BIT 0 (LSB) Bit 21 of address codeword BIT 1 (MSB) bit 20 of address codeword BIT 2 0 0 1 1 Table 5 Message word format BIT 1 BIT 2 BIT 3 message bits BIT 4 BIT 5 BIT 6 MSB BIT 3 0 1 0 1 RIC A B C D 1 BIT 5 0 = Data Receive; 1 = Data fail SYNC STATUS
PCF5001
Table 4
FUNCTION CODE
DUPLEX CALL BIT 7 BIT 6 1 = Duplex Call time-out active 0
BIT 0 LSB Note
BIT 7(1) error flag
1. Bit 7 = 1, if message codeword could not be corrected. Table 6 Termination word format BIT 1 0 BIT 2 1 BIT 3 0 BIT 4 0 BIT 5 0 BIT 6 0 BIT 7(1) error flag
BIT 0 0 Note
1. Bit 7 = 1, if call termination on error. 7.16 Data conversion into message blocks, seven bits in length. After adding the error flag they are transferred as message words. When a conversion from numeric format to ASCII takes place, the received message codewords are split into blocks, four bits in length. Each four bit block is converted to a seven bit block as shown in Table 8. After adding the error flag they are transferred as message words.
The PCF5001 automatically converts message codewords received in numeric or alphanumeric format into ASCII format. Depending on SPF13 and the function bit setting in the received address codeword a conversion takes place as shown in Table 7. When a conversion from alphanumeric format to ASCII takes place, the received message codewords are split Table 7 Message data conversion FUNCTION BITS SPF13 BIT 20 (MSB) 0 1 1 1 Note 1. X = don't care. X(1) 0 X(1) 1
MESSAGE FORMAT BIT 21 (LSB) X(1) 0 1 X(1) numeric numeric alphanumeric alphanumeric
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
Table 8 Numeric format to ASCII conversion 4-BIT BLOCK CHARACTER LSB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 7.17 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSB 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 `0' `1' `2' `3' `4' `5' `6' `7' `8' `9' `*' `U' `' `-' `]' `[' LSB 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 7-BIT BLOCK
PCF5001
MSB 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
Memory Organization
The PCF5001 POCSAG decoder contains non-volatile EEPROM memory to store four user addresses, two frame numbers and specially programmed function bits (SPF01 to SPF32) for decoder application configuration. The EEPROM is organized as three arrays of 38 bits each as shown in Fig.17. A user address (or RIC) in POCSAG code comprises of 21 bits, but the three least significant bits are coded in the frame number and therefore not explicitly transmitted. In the PCF5001, addresses A/B and C/D must share the same frame number: addresses A and B reside in frame FR1 (FR10, FR11 and FR12), addresses C and D reside in frame FR2 (FR20, FR21 and FR22). Figure 18 shows an example of decimal address to EEPROM content conversion. Each address must be explicitly enabled by resetting of the associated enable bit.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
EEPROM ARRAY 1
BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 A17 A16 A15 A14 A13 A12 A11 A10 A09 BIT9 A08 BIT8 A07 BIT7 A06 BIT6 A05 BIT5 A04 BIT4 A03 BIT3 A02 BIT2 A01 BIT1 A00 BIT0 ENA
BIT37 BIT36 BIT35 BIT34 BIT33 BIT32 BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT19
B17
B16
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B00
ENB
EEPROM ARRAY 2
BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 C17 C16 C15 C14 C13 C12 C11 C10 C09 BIT9 C08 BIT8 C07 BIT7 C06 BIT6 C05 BIT5 C04 BIT4 C03 BIT3 C02 BIT2 C01 BIT1 C00 BIT0 ___ ENC
BIT37 BIT36 BIT35 BIT34 BIT33 BIT32 BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT19
D17
D16
D15
D14
D13
D12
D11
D10
D09
D08
D07
D06
D05
D04
D03
D02
D01
D00
END
EEPROM ARRAY 3
BIT18 BIT17 BIT16 BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
SPF13 SPF12 SPF11 SPF10 SPF09 SPF08 SPF07 SPF06 SPF05 SPF04 SPF03 SPF02 SPF01 FR20
FR21
FR22
FR10
FR11
FR12
BIT37 BIT36 BIT35 BIT34 BIT33 BIT32 BIT31 BIT30 BIT29 BIT28 BIT27 BIT26 BIT25 BIT24 BIT23 BIT22 BIT21 BIT20 BIT19
SPF32 SPF31 SPF30 SPF29 SPF28 SPF27 SPF26 SPF25 SPF24 SPF23 SPF22 SPF21 SPF20 SPF19 SPF18 SPF17 SPF16 SPF15 SPF14
MCD469
A00 represents the MSB of RIC A, B00 is the MSB of RIC C, etc. FR10 represents the MSB of Frame 1 (valid for RICs A and B), FR20 is the MSB of Frame 2 (RICs C and D).
Fig.17 EEPROM memory organization.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
address decimal value (example: RIC A) RIC A = 1 2 4 6 8
binary equivalent (18 + 3 bit available) 000000011000010110100
EEPROM Allocation A00 0 A01 0 A02 0 A03 0 A04 0 A05 0 A06 0 A07 1 A08 1 A09 0 A10 0 A11 0 A12 0 A13 1 A14 0 A15 1 A16 1 A17 0
FR10 FR11 FR12 1 0 0
MCD470
A00 is the MSB of RIC A, FR10 is the MSB of Frame 1.
Fig.18 Decimal address to memory contents conversion example.
7.18
Description of the Special Programmed Function (SPF) bits
The following features can be selected by appropriate programming of the special programmed function bits as shown in Table 9. Table 9 Special Programmed Function (SPF) bits SPF SPF01 SPF02 SPF03 SPF04, SPF05 00 01 10 11 BIT 0 1 0 1 0 1 Alert-only pager mode. Display pager mode. 512 bits/s data rate. 1200 bits/s data rate, possible with 76.8 kHz crystal only. 32768 Hz crystal configuration. 76800 Hz crystal configuration. Receiver establishment time (depending on data rate). 7.8 ms/512 bits/s; 53.3 ms/1200 bits/s. 15.6 ms/512 bits/s; 6.7 ms/1200 bits/s. 31.3 ms/512 bits/s; 13.3 ms/1200 bits/s. 62.5 ms/512 bits/s; 26.7 ms/1200 bits/s. FUNCTION
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
SPF SPF06, SPF07
BIT 00 01 10 11 30 s. 60 s. 120 s. 240 s.
FUNCTION Duplicate call suppression time-out and out-of-range hold-off time-out.
SPF08 SPF09 SPF10 SPF11 SPF12 SPF13
0 1 0 1 0 1 0 1 0 1 0 1
Voltage converter disabled, if SPF01 = 1 (`display pager' mode). Voltage converter enabled, if SPF01 = 1 (`display pager' mode). SILENT override on address C disabled. SILENT override on address C enabled. SILENT override on address D disabled. SILENT override on address D enabled. Vibrator output disabled. Vibrator output enabled. Call termination criteria combination method (note 1). Call termination criteria defined by SPF13. Numeric data deformatting, call termination on first uncorrectable codeword. Numeric data deformatting on function code 00 only, call termination on two uncorrectable codewords. Duplicate call suppression disabled. Duplicate call suppression enabled. Out of range indication at OL output disabled, hold-off period is zero regardless of SPF06 and SPF07 setting. Out of range indication at OL output enabled, hold-off period is according to SPF06 and SPF07 setting. Repeat alert disabled. Repeat alert enabled. Call data output on OL disabled. Call data output on OL enabled. Spare. Program always 0. Spares. Alerter frequency 2048 Hz. Alerter frequency 2731 Hz. Frequency reference output 16384 Hz if SPF01 = 1 (`display pager' mode). Frequency reference output 32768 Hz if SPF01 = 1 (`display pager' mode).
SPF14 SPF15
0 1 0 1
SPF16 SPF17 SPF18 SPF19 SPF20 to SPF30 SPF31 SPF32 Note 1. Call termination on:
0 1 0 1 - - - 0 1 0 1
a) First codeword immediately following address codeword uncorrectable. b) Two consecutive codewords uncorrectable.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
7.19 EEPROM Write operation 7.21
PCF5001
Read-back operation via Microcontroller Interface
The program mode is entered in OFF status by setting the PD input LOW and the PS input HIGH at any time. The `program' mode is left and normal operation resumed by either removing the power supply or setting the PD input HIGH after the 38th data bit while continuing to clock the PS input. The three EEPROM arrays can be programmed in any order. Selection of array is made during the second and third pulse on the PS input. The `program' mode has to be left after programming of each array. After entering the `program' mode, keeping input PD LOW during the first pulse on PS selects Memory Write operation. After selection of the current array an erase cycle of duration tPEW has to be carried out, during which the supply voltage at VSS input must be at least VPG. Program data for the selected array is entered bit by bit using PD as data input and the rising edge on PS as data strobe pulse. See Fig.19 for timing during an EEPROM write operation. After the last bit a special write cycle of duration tPEW has to be carried out again, during which the supply voltage at VSS input must be VPG. During conditions when the supply voltage is increased to VPG the maximum DC ratings at Vref must not be exceeded. When the on-chip voltage converter is enabled a voltage regulator diode or a damping resistor of sufficiently low impedance has to be connected between Vref and VSS to limit the voltage level at Vref during program operation. 7.20 EEPROM Read operation
In `display pager' mode, the PCF5001 is capable of delivering the EEPROM contents to an external microcontroller using the serial interface outputs DO and DS. The EEPROM data transfer mode is selected by applying a LOW to input ON and a HIGH to input SK while pulsing the SR input, and the interface is enabled (IE is HIGH). The data transfer is started by a logic HIGH level on SR. The HIGH level on SR must be removed before the end of the tenth output byte, otherwise the transfer is aborted and restarted. The minimum pulse duration corresponds with tSPD in the status interrogation timing (see Fig.7). The transfer is organized as 15-byte transfers. The contents of each array are extended to 40 bits by trailing zeros. The EEPROM data transfer starts with array 1, bit 0. A valid data bit at DO is indicated by a LOW-level on DS as shown in Fig.20. During EEPROM Read-back operation, the PCF5001 configuration and the outputs FL, OL are undefined. After completion of the Read-Back operation, the PCF5001 will re-enter the programmed configuration. 7.22 Voltage converter
The PCF5001 contains a switched capacitor-type on-chip voltage converter, which can provide doubled supply voltage to the external microcontroller and display control devices. The microcontroller interface signals are level shifted accordingly. A capacitor of 100 nF (CS) must be connected between pins CP and CN while a load capacitor of 10 F is connected to Vref as shown in Fig.23. The voltage converter operates in `display pager' mode only, when enabled by programming SPF08 (see Table 9).
After entrance to the `program' mode, keeping input PD HIGH during the first pulse on PS selects Memory Read operation. After selection of the current array the programmed data is output bit-by-bit using PD as data output. A positive edge on PS input switches to the next bit. See Fig.19 for timing during an EEPROM read operation.
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1997 Mar 04
Philips Semiconductors
POCSAG Paging Decoder
PD SEL1 1.5 MHz 1.5 MHz
WRITE SEL0
BIT0
BIT1
BIT2
BIT37
PS 3 4 t PEW t PCL t PCH t PEW 5 6 7 42 t PDH 43 44 45
1
2
t RES
t PSI
27
SEL1 BIT0 BIT1 BIT2 BIT37
MCD471 - 2
PD
READ
SEL0
PS 3 t PDH t PRS t PCL t PCH t PSO 4 5 6 7 41 42 43 44 45
1
2
t RES
t PSI
Product specification
PCF5001
Fig.19 EEPROM read/write timing.
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
SR
DO
ENA
B17
ENC
D17
FR12
SPF 32
DS
MCD472
t SDD
t DSE
Fig.20 EEPROM data transfer to microcontroller timing.
7.23
Test modes of the decoder
7.23.2
PAGER TEST MODE (TYPE APPROVAL MODE)
The decoder supports two test modes, which are intended for use during pager production and type approval tests. 7.23.1 BOARD TEST MODE
`Pager test' mode is entered by reception of a valid call while `board test' mode is active, see above. In `pager test' mode: 1. Call alert cadences are terminated after 2 seconds 2. Duplicate call suppression is disabled. Exit from `pager test' mode is achieved by disconnecting the power supply from the decoder.
`Board test' mode is selected by setting the PD input LOW at any time. In this test mode the following features are provided: 1. Receiver enable output is set constantly HIGH 2. Output AL is activated by a LOW-level on ON input 3. Output AH is activated by a HIGH-level on SR input 4. Outputs OL and OM are activated by a HIGH-level on SK input. Exit from `board test' mode is achieved by setting input PD HIGH.
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VSS VPG Vn Vn1 Ptot PO II(max) IO(max) PARAMETER supply voltage programming supply voltage voltage on pins FL, DS, DO, OR, BL, AI, ON, SK, SR and IE input voltage on any other pin total power dissipation power dissipation per output maximum input current (any input) maximum output current any output except AL output AL Tamb Tstg Note 1. VDD is connected to the substrate (see Fig.1), and is referred to as common, 0 V. 9 DC CHARACTERISTICS VDD = 0 V; VSS = -2.7 V; Vref = 2.7 V; Tamb = 25 C; unless otherwise specified. Quartz crystal parameters: f = 76800 Hz; RS(max) = 40 k; CL = 12 pF. Decoder Mode programmed as Alert-only (SPF01 = 0). SYMBOL Supply VSS supply voltage voltage converter disabled; all outputs open-circuit Tamb = -10 to +85 C Tamb = -40 to +85 C ISS VPG IPG supply current programming supply voltage programming supply current note 1 note 2 -1.5 -1.8 - -4.5 - -2.7 -2.7 -60 -5.0 -500 PARAMETER CONDITIONS MIN. TYP. operating ambient temperature storage temperature - - -40 -55 20 70 +85 +125 CONDITIONS note 1 MIN. +0.5 -5.5 +0.8 +0.8 - - - -
PCF5001
MAX. -8.0 Vref - 0.8 VSS - 0.8 250 100 10 V V V V
UNIT
mW mW mA mA mA C C
MAX.
UNIT
-6.0 -6.0 -100 -5.5 -
V V A V A
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
SYMBOL Inputs VIL1 VIL2 VIH1 VIH2 II
PARAMETER
CONDITIONS
MIN. - - - -
TYP. - -
MAX.
UNIT
LOW level input voltage PD, PS, DI, BS, TS, TT and X1 LOW level input voltage AI, ON, SR, SK and IE HIGH level input voltage PD, PS, DI, BS, TS, TT and X1 HIGH level input voltage AI, ON, SR, SK and IE input current BS, PS, TS and TT PD DI DI ON and SK AI and SR VI = VDD VI = VSS VI = VDD; RE = 0 VI = VDD; RE = 1 VI = VSS VI = VDD
0.7VSS 0.7Vref - -
V V V V
0.3VSS 0.3Vref
7.0 -9.0 7.0 0 -0.5 7.0 2
- - - - -0.8 - -
20.0 -24.0 20.0 0.5 -1.1 20.0 -
A A A A A A pF
Ci
input capacitance BS, DI, PD, PS, TS, TT, AI, ON, SR, SK, IE and X1
Outputs IOL LOW level output current OL, OM and AH DO, DS, BL, FL and OR AL RE IOH HIGH level output current OL, OM and AH DO, DS, BL, FL and OR AL RE Oscillator CXO gm VPU Notes 1. All inputs = VSS; voltage converter off; all outputs open-circuit. 2. See Section 7.19 and Chapter 8 for limitations of Vref when programming while the voltage converter is enabled. output capacitance X2 oscillator transconductance power-up reset threshold voltage VSS = -1.5 V VSS = -6.0 V - 15 25 - 40 29 39 -1.2 - 43 55 - pF S S V VOH = -1.35 V VOH = -1.35 V AL high-impedance VOH = -0.5 V -0.8 -100 - -1.0 - - - - -1.8 - -0.2 - mA A A mA VOL = -1.35 V VOL = -1.35 V VOL = -1.5 V VOL = 2.2 V 100 100 17.5 200 - - - - - - - - A A mA A
1997 Mar 04
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
10 DC CHARACTERISTICS (WITH VOLTAGE CONVERTER) VDD = 0 V; VSS = -3.0 V; Vref = -6.0 V; Tamb = 25 C. Quartz crystal parameters: f = 76800 Hz; RS(max) = 40 k; CL = 12 pF. Decoder Mode programmed as Display Pager (SPF01 = 1). Voltage converter enabled (SPF08 = 1); CS = 100 nF. SYMBOL Supply VSS Vref(0) Vref Iref Inputs II input current AI, ON, SR and SK ON and SK SR VI = Vref VI = VDD VI = VDD; Vref = -6.0 V - - - 0 0 17 supply voltage VSS = -3.0 V VSS = -2.0 V; Iref = 250 A VSS = -2.0 V; Vref = -2.7 V VSS = -3.0 V; Vref = -4.5 V -1.5 -5.8 -3.0 400 600 - - -3.5 600 900 PARAMETER CONDITIONS MIN. TYP.
PCF5001
MAX. -3.0 -6.0 - - -
UNIT
V
Voltage converter output voltage; no load output voltage output current V V A A
-0.5 0.5 -
A A A
11 AC CHARACTERISTICS VDD = 0 V; VSS = -2.7 V; Tamb = 25 C. Quartz crystal parameters: f = 32768 or 76800 Hz; RS(max) = 40 k; CL = 12 pF. Decoder Mode programmed as Display or Alert-only Pager (SPF01 = 1 or 0). SYMBOL Alert frequency fAL fAWH fAWL fAL fAWH fAWL fFL alert frequency high alert warble frequency low alert warble frequency alert frequency high alert warble frequency low alert warble frequency output frequency reference at FL SPF32 = 0 SPF32 = 1 SPF31 = 1 SPF31 = 0 - - - - - - - - 2048 1024 16 2731 1365 16 16384 32768 - - - - - - - - Hz Hz Hz Hz Hz Hz Hz Hz PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
SYMBOL Call alert duration tALT tALL tALH tALC tALP tALD tRPT tRCR tRCP tRPD tSTON tSTOF tSUA tORA tORD tBLAL tRXT tRXON fDO tDSD tDSE tDSW tTDO tDOS tDOH tBYD tCWD tST tSP tSTL tSPL tSDD
PARAMETER
CONDITIONS - - - see Fig.9 see Fig.9 see Fig.8 see Fig.11 see Fig.11 - -
MIN.
TYP.
MAX. - - - - - - 4 15 500 250 62.5 62.5 500 453 62.5 2 16
UNIT
time-out period alert time LOW (AL output only) alert time HIGH (AH and AL outputs) call alert cycle time call alert pulse duration call alert hold off period repeat alert duration repeat alert recurrence time repeat alert cycle time repeat alert pulse duration status alert time status alert delay start-up alert time out-of-range alert pulse width out-of-range alert time battery LOW-level alert time see Fig.10 see Fig.10 SPF02 = 0; see Fig.13 SPF02 = 1; see Fig.13 see Fig.12 see Fig.12
16 4 12 1 125 - - - - - - - - - - - - - 7.8
s s s s ms ms s s ms ms ms ms ms ms ms s s
52 - - - - - - - - - - - - - -
Receiver control RE transition time RE establishment time CL = 5 pF SPF04 = 0; SPF05 = 1 100 62.5 - 495 1150 250 100 135 - 1225 - - 615 495 495 10 ns ms
Data output data output rate strobe period call data strobe period EEPROM data data strobe pulse width data output transition time data output set-up time data output hold time consecutive byte delay inter-codeword delay start condition set-up time stop condition set-up time start bit period OL output stop bit period OL output SPF output delay see Fig.20 1200 bits/s numeric message see Fig.15 see Fig.15 see Fig.15 see Fig.20 see Fig.15 CL = 10 pF; see Fig.15 see Fig.15 see Fig.15 2048 - 488 - - - - - - - - - 488 - bits/s s s s ns s s s s s s s s ms 480 200 230 - - 115 1210 3420 4750 595 480 480 1
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Philips Semiconductors
Product specification
POCSAG Paging Decoder
12 TIMING CHARACTERISTICS VDD = 0 V; VSS = -2.7 V; Tamb = 25 C. Quartz crystal parameters: f = 32768 or 76800 Hz; RS(max) = 40 k; CL = 12 pF. Decoder Mode programmed as Display or Alert-only Pager (SPF01 = 1 or 0). SYMBOL PARAMETER CONDITIONS - - - tBIT tBIT - - - 1125 - SPF02 = 1; fosc = 76800 Hz - - - 480 - - MIN. TYP.
PCF5001
MAX. - - 100 - - - - - - - - - - - - 35 - - - - 15 - - -
UNIT
Operating frequency dependent fosc tTDI tDI1 tDI0 fDI tBIT tCW tPA tBAT fDI tBIT tCW tPA tBAT tSDB tSTP tSTD tIEH tSTH tSPD tSTP tSTD tIEH tSTH tSPD oscillator frequency data input transition time data input logic 1 data input logic 0 data input rate bit period codeword duration preamble duration batch duration data input rate bit period codeword duration preamble duration batch duration SPF03 = 0 SPF03 = 1 see Fig.21 see Fig.21 see Fig.21 SPF02 = 0 32768 76800 - - - 512 1.9531 62.5 - 1062.5 1200 833.3 26.7 - 453.3 Hz Hz s
bits/s ms ms ms ms bits/s ms ms ms ms
Alert only mode (SPF01 = 0) switch debounce period 62.5 - - - - - - - - - - ms s s s s s s s s s s
Display pager mode (SPF01 = 1); see Figs 6 and 7 status set-up time status change delay interface enable hold time status hold time status pulse duration status set-up time status change delay interface enable hold time status hold time status pulse duration fosc = 76800 Hz fosc = 32768 Hz 35 - 35 35 35 15 - 15 15 15
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33
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
handbook, halfpage
tDI1
tDI0
t TDI
MGL100
Fig.21 Data input timing.
13 PROGRAMMING CHARACTERISTICS VDD = 0 V; VSS = VPG = -5.0 V (see notes 1, 2 and 3); Vref = VSS; pins 2 and 3 open-circuit; Tamb = 25 C. Quartz crystal parameters: f = 32768 Hz; RS(max) = 40 k; CL = 12 pF. Decoder in OFF status. SYMBOL PARAMETER CONDITIONS MIN. - - 1.5 10000 - - - - - - - TYP. MAX. - - 2.0 - - - - 35 - 35 - UNIT s ms MHz - years s s s s s s
Programming; see Fig.19 tRES tPEW fEW tEW tDR tPCH tPCL tPRS tPSI tPSO tPDH Notes 1. VSS = VPG only required during erase/write (tPEW in Fig.19), otherwise VSS(min) = -1.5 V. 2. Maximum voltage for programming (VPG) is -5.5 V. 3. See Section 7.19 and Chapter 8 for limitations of Vref when programming while the voltage converter is enabled. 4. EEPROM programming is also possible at higher frequencies (76.8 kHz or 153.6 kHz). The timings shown then become proportionally smaller. power-up reset pulse width erase/write time erase/write frequency erase/write cycles data retention time data clock HIGH time data clock LOW time read set-up time data set-up time on input data set-up time on output data hold time Tamb = 85 C note 4 note 4 note 4 note 4 note 4 note 4 note 4 35 10 1.0 1000 10 65 65 - 35 - 35
1997 Mar 04
34
1997 Mar 04
M status reset 10 pF VDD IE SR AL X1 32768 Hz or 76800 Hz X2 OL DI AH
Philips Semiconductors
14 APPLICATION INFORMATION
POCSAG Paging Decoder
antenna
VCC
RECEIVER
1.5V 1.5V
data output RE OM BS ON SK PD PS V REF VSS
PCF5001
35
OFF ON SIL
Rx control
battery low indicator
V EE
MLB046
Product specification
PCF5001
Fig.22 Alert-only pager application example.
1997 Mar 04
M
Philips Semiconductors
LCD
VDD AL FL X1 DS DO OR X2 DI ON RE SR SK IE V REF AH V SS PD PS VSS OM OL BS CN CP BL AI 1.5V 1.5V 10 F V DD
10 pF
POCSAG Paging Decoder
antenna
VCC
RECEIVER
32768 Hz or 76800 Hz
data output
PCF5001
MICRO CONTROLLER
Rx control
36 Fig.23 Display-pager application example.
battery low indicator
V EE
CS 100 nF
switch matrix
MLB047
Product specification
PCF5001
Philips Semiconductors
Product specification
POCSAG Paging Decoder
15 PACKAGE OUTLINES SO28: plastic small outline package; 28 leads; body width 7.5 mm
PCF5001
SOT136-1
D
E
A X
c y HE vMA
Z 28 15
Q A2 A1 pin 1 index Lp L 1 e bp 14 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 18.1 17.7 0.71 0.69 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT136-1 REFERENCES IEC 075E06 JEDEC MS-013AE EIAJ EUROPEAN PROJECTION
ISSUE DATE 91-08-13 95-01-24
1997 Mar 04
37
Philips Semiconductors
Product specification
POCSAG Paging Decoder
PCF5001
LQFP32: plastic low profile quad flat package; 32 leads; body 7 x 7 x 1.4 mm
SOT358-1
c
y X
24 25
17 16 ZE
A
e E HE wM A A2 A 1
Q (A 3) bp Lp L
pin 1 index 32 1 e bp D HD wM B vM B 8 ZD vM A 9 detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.4 0.3 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.8 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 Q 0.69 0.59 v 0.2 w 0.25 y 0.1 Z D (1) Z E (1) 0.9 0.5 0.9 0.5 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT358 -1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 93-06-29 95-12-19
1997 Mar 04
38
Philips Semiconductors
Product specification
POCSAG Paging Decoder
16 SOLDERING 16.1 Introduction 16.3.2 SO
PCF5001
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 16.2 Reflow soldering
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 16.3.3 METHOD (LQFP AND SO)
Reflow soldering techniques are suitable for all LQFP and SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 16.3 16.3.1 Wave soldering LQFP
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering LQFP packages LQFP48 (SOT313-2), LQFP64 (SOT314-2) or LQFP80 (SOT315-1). 1997 Mar 04 39
Philips Semiconductors
Product specification
POCSAG Paging Decoder
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF5001
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Mar 04
40
Philips Semiconductors
Product specification
POCSAG Paging Decoder
NOTES
PCF5001
1997 Mar 04
41
Philips Semiconductors
Product specification
POCSAG Paging Decoder
NOTES
PCF5001
1997 Mar 04
42
Philips Semiconductors
Product specification
POCSAG Paging Decoder
NOTES
PCF5001
1997 Mar 04
43
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2870, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
437027/00/05/pp44
Date of release: 1997 Mar 04
Document order number:
9397 750 01626

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